1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device comprising a BiCMOS transistor.
2. Description of the Related Art
A principal portion of a recent electronic apparatus, such as a telecommunication device is mostly composed of a large scale integrated circuit (LSI) in which electric circuits constituted by a large number of transistors and resistors are integrated within a single chip.
Additionally, there is a strong demand for miniaturization of a telecommunication device, in particular a radio terminal device. Moreover, it is also urged recently to accelerate the operation speed of this kind of electronic device. Under these circumstances, a BiCMOS transistor which is a composite device comprising a CMOS transistor suited for high integration and a bipolar transistor suited for high speed operation has been noticed as being important for meeting these demands.
FIGS. 11A to 13C show cross-sectional views illustrating a manufacturing step of a high speed BiCMOS transistor according to a first embodiment of the conventional technique. Referring to FIG. 11A, an n.sup.+ -type diffusion layer 2 is formed on the surface of a p-type silicon substrate 1, and then an n-type epitaxial layer 3 is deposited all over the p-type silicon substrate 1.
Subsequently, a p-type well 4 and an n-type well 5 each extending down to the p-type silicon substrate 1 are selectively formed in the n-type epitaxial layer 3 as shown in FIG. 11B.
After a shallow trench insulating layer 6a is formed as shown in FIG. 11C, a deep trench insulating layer 7 is formed to isolate the n.sup.+ -type diffusion layer 2 from the p-type well 4 as well as from the n-type well 5. Then, the region of n-type epitaxial layer 3 to be formed into a bipolar transistor is partitioned by the formation of a shallow trench insulating layer 6b.
After forming a gate oxide layer 8 on the p-type well 4 as well as on the n-type well 5 as shown in FIG. 12A, an impurity is ion-implanted in the channel region 13 of the p-type well 4 as well as in the channel region 14 of the n-type well 5 so as to obtain a desired threshold voltage in each of these region.
Then, as shown in FIG. 12B, after a gate electrode 10 is formed on the gate oxide layer 8, an n.sup.+ -type diffusion layer 9 for forming a portion of collector, an n.sup.+ -type silicon layer 11 functioning as a collector-extracting electrode and a p.sup.+ -type silicon layer 12 functioning as a base-extracting electrode are formed respectively. Thereafter, an ion implantation is performed using the gate electrode 10 as a mask, thereby forming source/drain regions 15 and 16 on the surfaces of the p-type well 4 and the n-type well 5, respectively.
Further, the surface of the resultant substrate is deposited all over with a silicon oxide layer 17, on which a silicon nitride layer 18 is subsequently deposited as shown in FIG. 12C.
Then, an opening is formed by selectively etching the silicon nitride layer 18, the silicon oxide layer 17 and the p.sup.+ -type silicon layer 12, whereby exposing the surface of a region of the n-type epitaxial layer 3 in which an emitter and an inner base are to be formed in a subsequent step.
Subsequently, a silicon oxide layer 20 is formed on the bottom and side wall of the opening, and an impurity is ion-implanted through this silicon oxide layer 20 in the surface of the n-type epitaxial layer 3 to form an inner base region 21. Thereafter, a thermal treatment is performed to allow the n-type impurity contained in the p.sup.+ -type silicon layer 12 to diffuse into the n-type epitaxial layer 3, thus forming an outer base 19.
Then, after a silicon nitride layer for forming a side wall 22 is deposited all over the resultant substrate as shown in FIG. 13B, this silicon nitride layer is etched back to leave the side wall on the inner wall of the opening and at the same time to remove a portion of silicon oxide layer 20 disposed over a region for an emitter 24. After an n.sup.+ -type polycrystalline silicon layer for forming an emitter-extracting electrode 23 is deposited all over the resultant substrate, the n-type impurity in this n.sup.+ -type polycrystalline silicon layer is allowed to diffuse into the n-type epitaxial layer 3 to form an emitter 25. Then, the n.sup.+ -type polycrystalline silicon layer is patterned to form the emitter-extracting electrode 23.
Finally, the silicon nitride layer 18 and the silicon oxide layer 17 are etched away as shown in FIG. 13C to expose the upper surfaces of the source/drain regions 15 and 16, the base-extracting electrode 12 and the collector-extracting electrode 11. Then, the resultant substrate is deposited all over the surface thereof with a metallic layer, which is subsequently patterned forming a metallic wiring 24 (a source/drain electrode, a base electrode, a collector electrode and an emitter electrode), thus completing the basic structure of BiMOS transistor.
If LOCOS is employed as an element isolation in this case, a parasitic capacity is generated due to an interaction among the base-extracting electrode 12 (an upper capacitor electrode), a bird's beak-shaped insulating film (a capacitor insulating layer) and the outer base 19 (a lower capacitor electrode). In the example explained above however, the element isolation is effected by means of a trench isolation, so that a thin portion (bird's beak-shaped) as in the case of LOCOS would not be formed in the insulating layer for element isolation, thus making it possible to prevent the generation of the parasitic capacity. As explained above, it is possible according to the BiCMOS transistor making use of a trench isolating insulating layer to inhibit the generation of parasitic capacity, and therefore to fully realize a high speed performance of a bipolar transistor.
FIG. 14 shows, as an example of a second embodiment of the conventional technique, a cross-sectional view of the structure of a high speed BiCMOS transistor. This BiCMOS transistor can be manufactured as follows.
First, an n.sup.+ -type diffusion layer 32 is formed on the surface of a p-type silicon substrate 31, and then an n-type epitaxial layer 33 is deposited all over the p-type silicon substrate 31.
Subsequently, a trench isolating insulating layer 37 is formed for an element isolation after one region of the n-type epitaxial layer 33 for forming an n-type MOS transistor is converted into a p-type well 34 of predetermined impurity concentration, and another region of the n-type epitaxial layer 33 for forming an p-type MOS transistor is converted into an n-type well 34 of predetermined impurity concentration.
After the region for forming an npn-type bipolar transistor as well as the region for forming a p-type MOS transistor are covered with a protecting film (not shown), a p-type impurity ion implantation is performed so as to adjust the threshold voltage of the n-type channel region. Then, the protecting film covering the region for forming a p-type MOS transistor is removed, and the region for forming an n-type MOS transistor is covered with a protecting film (not shown). Then, an n-type impurity ion implantation is performed so as to adjust the threshold voltage of the p-type channel region. After removing the protecting film covering the region for forming an n-type MOS transistor, thus only the region for forming the npn-type bipolar transistor being covered with a protecting film, the whole surface of the resultant substrate is oxidized to form an oxide layer that is to become a gate oxide layer 40.
After a polycrystalline silicon layer 41 to be utilized as a gate electrode layer is deposited on the gate oxide layer 40, the polycrystalline silicon layer 41 which is an intrinsic semiconductor is turned into an n.sup.+ -type semiconductor by means of a phosphorus diffusion for example. After being deposited all over with a silicon layer 42, the n.sup.+ -type polycrystalline silicon layer 41 and the silicon oxide layer 42 are patterned, thus forming a gate electrode.
Then, a side wall 43 consisting for example of a silicon nitride layer is formed on the inner wall of the gate electrode. Subsequently, an n-type impurity such as As ion is implanted to form an n.sup.+ -type source/drain diffusion layer 44 of n-type MOS transistor, and at the same time, a p-type impurity such as B ion is implanted to form a p.sup.+ -type source/drain diffusion layer 45 of p-type MOS transistor, thus accomplishing a CMOS transistor.
Subsequently, a bipolar transistor is manufactured as follows. First of all, a protecting film covering the npn bipolar transistor is removed, and then only the region of CMOS is covered with a protecting film. A p.sup.+ -type polycrystalline silicon layer that is to become a base electrode-extracting electrode 46 is deposited all over and patterned in the form of a base electrode-extracting electrode. Thereafter, a silicon oxide layer 47 is deposited all over the surface of the resultant substrate.
Then, in order to minimize the collector resistance, an n.sup.+ -type diffusion layer (collector) 48 extending from the surface of the collector-extracting portion to the n.sup.+ -type buried layer 32 is formed. Next, the silicon oxide layer 47 and the p.sup.+ -type polycrystalline silicon layer 46 are etched away to expose the surface of an n-type epitaxial layer 33, thus forming an opening 49, through which a p-type impurity ion is implanted forming an inner base 50.
After depositing an insulating layer such as a silicon nitride layer all over the surface of the resultant substrate, an anisotropic etching of this insulating layer is performed to form a side wall 51. After a third polycrystalline silicon layer for forming an emitter-extracting electrode 52 is deposited, an n-type impurity such as arsenic ion is ion-implanted into this third polycrystalline silicon layer.
Then, the n-type impurity in the third polycrystalline silicon layer is diffused to form an emitter 53, and then the third polycrystalline silicon layer is patterned to form an emitter-extracting electrode 52. After an overall deposition of an insulating interlayer 54 is performed, a contact hole to each of the emitter, base, collector, source, gate and drain is respectively formed through the insulating interlayer 54.
Finally, an aluminum layer is deposited all over the surface of the resultant substrate, and then this aluminum layer is patterned to form electrodes for each of the emitter electrode 55, base electrode 56, collector electrode 57, source electrode 58, gate electrode 59 and drain electrode 60, thus completing a BiCMOS transistor.
However, there is a problem in the case of the first embodiment of the conventional technique that a leak current is more likely to be generated at the field edge portion of a MOS transistor. The cause of this leak current may be ascribed to a deterioration in adhesion between the shallow trench insulating layer 6a and the substrate as a result of the formation of a crystal defect in the substrate (a portion of the substrate which contacts with the shallow trench insulating layer 6a) during the step of forming the shallow trench insulating layer 6a. In the case of a bipolar transistor however, there would not be raised such a problem of leak current at the field edge portion, since there is disposed a deep trench insulating layer 7.
Moreover, in the case of a BiCMOS transistor according to the first embodiment of the conventional technique, there is another problem that the number of treatment step is increased, since it requires the formations of a deep trench insulating layer 7 and a shallow trench insulating layer 6b after the formation of a shallow trench insulating layer 6a. Namely, since the step of forming an element isolation layer of a MOS transistor is required to be performed in separate to the step of forming an element isolation layer of a bipolar transistor according to the first embodiment of the conventional technique, it is difficult to reduce the number of treatment step.
On the other hand, there is a problem also in the manufacturing method of a BiCMOS transistor according to the second embodiment of the conventional technique as explained below.
First, since a MOS transistor is required to be formed in separate to a bipolar transistor, the process for forming a BiCMOS transistor is complicated and takes a many number of steps. One of the reasons for forming a MOS transistor in separate to a bipolar transistor is a difference in structure between the MOS transistor and the bipolar transistor. Namely, a gate electrode is required to be contacted to a substrate through a gate oxide layer, whereas in the case of the base-extracting electrode and emitter-extracting electrode, they are required to be directly contacted to the substrate.
There is another problem that the profile of impurity concentration in the source/drain region or in the channel region which has been already formed may be altered as a result of a thermal treatment in the process of forming a bipolar transistor, thus causing the deterioration of the characteristic of semiconductor elements.